1. Field of the Invention
The present invention relates in general to the field of information processing, and more specifically to a signal processing system and method for generating a clock signal using a low-bandwidth phase-locked loop.
2. Description of the Related Art
Phase-locked loops are widely used in integrated circuits to provide an output signal in a predetermined phase relationship with a reference signal. The phase-locked loop output signal is a multiple of the reference signal. FIG. 1 depicts a classical phase-locked loop 100. The phase detector 102 compares a reference signal Ref having a frequency fref with a phase-locked loop feedback signal FB having a frequency fVCO/N and generates a phase error signal E, where N is a positive real number. Thus, the phase-locked loop 100 increases the frequency fref of reference signal Ref by a factor of N and maintains phase-alignment with the reference signal Ref. The value of the phase error signal represents a difference between phases of the reference signal Ref and the feedback signal FB. The reference signal Ref typically originates from a signal source that produces a periodic signal such as a crystal or ring oscillator. The loop filter 104 acts as a low-pass filter to smooth the phase error signal.
Voltage controlled oscillator (VCO) 106 generates a periodic phase-locked loop output signal PLLOUT having a frequency fVCO=fref×N. The filtered phase error signal E is an oscillator control signal OCS that regulates the frequency of the phase-locked loop output signal PLLOUT. The VCO 106 responds to the phase error signal E by increasing or decreasing the frequency of phase-locked loop output signal PLLOUT to match fref×N. The phase-locked loop output signal PLLOUT feeds back through frequency divider 108 to generate the feedback signal FB. Thus, the phase-locked loop 100 provides the output signal PLLOUT that is intended to have a predefined phase relationship (such as phase alignment) with the reference signal Ref and is a multiple of reference signal Ref. Some embodiments of phase-locked loop 100 substitute a current controlled oscillator (ICO) for the VCO 106. The phase-locked loop 100 operates essentially in the same manner except that the loop filter 104 includes a transconductance amplifier to provide a current based control signal to control the phase-locked loop output signal PLLOUT of the VCO 106.
FIG. 2 depicts an illustrative digital-to-analog signal processing system 200 having a delta sigma modulator 202 that converts oversampled input signal DATA into a series of M-bit output signals, where M is an integer greater than or equal to one (1). In at least one embodiment, the average of the series of M-bit represents the input signal DATA. The digital-to-analog converter (DAC) 204 converts the digital output of delta sigma modulator 202 into an analog signal output signal y(t). The signal processing system 200 is particularly useful for audio applications. For audio applications, the bandwidth of interest for the input signal DATA is generally in the 0 Hz to 25 kHz region. The analog signal generated by DAC 204 can be used for many purposes, such as to drive audio speakers.
The delta sigma modulator 202 and DAC 204 are clocked by the phase-locked loop output signal PLLOUT of phase-locked loop 206. In at least one embodiment, phase-locked loop 206 operates in the same manner as phase-locked loop 100. Serial clock SCLK represents the reference signal used by phase-locked loop 206.
FIG. 3 depicts clock signal timing diagrams 300 of two clock signals typically present in an audio digital-to-analog signal processing system. Clock signal LRCK represents a ‘left-right’ clock and is also often referred to as a “frame clock”. The frame clock signal LRCK identifies sample rates and frames two channels of data that exist in a single data stream. Historically, the equally spaced pulses of frame clock signal LRCK have a fifty percent (50%) duty cycle with the peaks and valleys being assigned to respective left and right channels (or vice versa). Thus, in a two channel system, data received during a peak is assigned to the left audio channel, and data received during a valley is assigned to the right audio channel. The use of the frame clock signal LRCK can be expanded for use in other multi-channel systems by assigning multiple channels to each peak and valley of frame clock signal LRCK.
The serial clock SCLK, also referred to as a “bit clock”, is used to clock the shifting of data into or out of a serial data port. The frequency of the serial clock SCLK is directly proportional to a data sampling rate and data word length. The minimum serial clock SCLK frequency is twice the sampling rate times the number of bits in each data word.
The third clock signal (not shown) is a master clock. The master clock is used to derive the frame clock signal LRCK and, thus, has a fixed, proportional relationship to the frame clock signal LRCK.
Referring to FIGS. 2 and 3, the loop bandwidth of the phase-locked loop 200 sets the low-pass cutoff frequency of the VCO control signal. As the loop bandwidth of phase-locked loop 200 narrows, the phase-locked loop 200 becomes slower in responding to phase changes in the reference signal Ref and maintaining a lock on the reference signal Ref becomes more difficult.
The serial clock SCLK has a higher frequency relative to the frame clock signal LRCK. Thus, phase-locked loop 206 has a wide loop bandwidth to track the relatively high frequency serial clock SCLK. A wide bandwidth phase-locked loop 206 is desirable from an integrated circuit standpoint because capacitors in loop filter 104 are relatively small can often be implemented as part of the integrated circuit, i.e. ‘on-chip’.
However, the serial clock SCLK is not a particularly stable reference source relative to the master clock and the frame clock signal LRCK. Instability, such as jitter (i.e. phase changes) and frequency shifts, in the reference signal causes the phase-locked loop output signal PLLOUT to also reflect the instabilities of serial clock SCLK.
FIG. 4 depicts an illustrative digital-to-analog signal processing system 400 (DAC system 400) that uses a master clock MCLK as a reference signal for the wide bandwidth phase-locked loop 402. In at least one embodiment, phase-locked loop 402 operates in the same manner as phase-locked loop 100. The DAC system 400 includes delta sigma modulator 202 followed by a pulse-width modulation encoder 404 to convert the serial output of the delta sigma modulator 202 into a representation of the input signal DATA. DAC system 400 also includes a low-pass, digital finite infinite response (FIR) filter 406 typically having 64-taps or less to attenuate energy in out-of-band frequencies. The DAC 408 converts the digital output of the FIR filter 406 into an analog output signal y(t).
A crystal oscillator generates the master clock master clock MCLK. The master clock MCLK is typically more stable and has a higher frequency than the serial clock SCLK and provides a reliable reference signal to phase-locked loop 402. However, the DAC system 400 still uses the serial clock SCLK, the DATA signal, and the frame clock signal LRCK to convert the digital DATA signal into an analog signal. The addition of the master clock MCLK, while addressing the stability issues of the serial clock SCLK, adds an extra level of complexity, electromagnetic issues, and cost to an integrated circuit.
FIG. 5 depicts a Type III RC loop filter 500 which represents an exemplary loop filter of a phase-locked loop such as phase-locked loop 100. In general, the loop filter design can govern the response of a phase-locked loop. The phase error signal E from the phase detector controls the conductivity of switches 502 and 504. A charge pump 501 includes switches 502 and 504 to respectively source or sink current to the RC circuit 506. Switches 502 and 504 can be respective complimentary metal oxide semiconductor (CMOS) p-channel and n-channel transistors. If the phase error signal E indicates a phase increase (UP) is needed for the phase-locked loop output signal PLLOUT to match the phase of the phase-locked loop reference signal, switch 502 conducts to source charge to the RC circuit 506 while switch 504 is nonconductive (“off”). Otherwise, to decrease the phase of phase-locked loop output signal PLLOUT, switch 504 conducts to sink charge from RC circuit 506 while switch 502 is off. In one embodiment, the phase error signal E is split into non-overlapping signals E and Ē (i.e. the inverse of E) to respectively control the conductivity of switches 502 and 504
Equation [1] represents an open-loop, S-domain transfer function for loop filter 500:
                                                        H              ⁡                              (                s                )                                      open                    =                                    Icp              ×              Kvco              ×                              (                                  1                  +                                                            RC                      1                                        ⁢                    s                                                  )                                                    2              ⁢              π              ×              N              ×                                                s                  2                                ⁡                                  (                                                                                    RC                        1                                            ⁢                                              C                        2                                            ⁢                      s                                        +                                          C                      1                                        +                                          C                      2                                                        )                                                                    ,                            [        1        ]            where Icp is the charge pump source/sink current, Kvco is the VCO gain constant, R is a resistor value, C1 and C2 are capacitor values, N is the frequency division constant, and s is a Laplace complex variable.
From equation [1], for low frequency loop bandwidth operation, e.g. below approximately 5,000 Hz, the implementation and performance of RC loop filter 506 can exhibit several drawbacks. For example, the loop filter 500 produces an undesirable ripple in control signal oscillator control signal OCS at low frequencies, such as 48 kHz or less, and high divide ratios, such as 1024:1. Additionally, to achieve low bandwidth operation, capacitors values C1 and C2 will be too large to be implemented on-chip. In at least one embodiment, for an audio application, low bandwidth is at or below 20 kHz. For example, for Icp=10 μA, Kvco=40 MHz/V, and a loop bandwidth of 5 kHz, C1=1.2 nF, which is too large to practically integrate on-chip.
FIG. 6 depicts a dual charge pump, loop filter 600, which represents an exemplary loop filter of a phase-locked loop such as phase-locked loop 100. Embodiments of the components and operation of loop filter 600 are described in U.S. Pat. No. 6,690,240. The loop filter 600 includes a feed forward, reset path 602 to provide loop stabilization and includes an integration path 604. The transfer function of loop filter 600 is based on an average charge from charge pumps 606 and 608. Accordingly, the oscillator control signal OCS is a step function with minimal ripple. However, from the natural frequency equation [2], the phase-locked loop bandwidth is determined primarily from capacitor 614. So, as the corner bandwidth frequency decreases, the value Cint of capacitor 614 increases. For low frequencies, e.g. lower than 5 kHz, capacitor 614 is too large to be integrated on-chip and is, thus, implemented as a discrete component.
Additionally, the reset path 602 has two paths 610 and 612. The two paths 610 and 612 hold the input voltage of gm2 and separate switching noise from charge pump 606 from the ICO 616. However, any mismatch between capacitor Cprop1 and Cprop2 causes an undesirable tone at the switching frequency/2 in the phase-locked loop output signal PLLOUT.
                                          ω            n                    =                                                    Kico                ×                Icp                ×                gm                ⁢                                                                  ⁢                1                                            2                ⁢                π                ×                Cint                ×                N                                                    ,                            Equation        ⁢                                  [        2        ]            ωn is the natural frequency of loop filter 600, Icp is the charge pump 606 source/sink current, Kico is the ICO gain constant, Cint represents the value of integrating capacitor 614, N is the frequency division constant, and gm1 is a transconductance amplifier.